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What is Architecture (also instruction set architecture = ISA)?
The parts of a processor design that one needs to understand to write assembly code.
This usually consists of instruction set specification and registers.
Example ISAs are x86, MIPS, ARM, ...
We will be using x86 in this course.
Does binary code that was written for Intels early x86-16 processors run on the newest x86-64 processors?
Yes
Can new code run on old processors?
It depends on compiler flags.
What are ISA SIMD (Single Instruction Multiple Data) Vector Extensions?
Extension of the ISA. Data types and instructions for the parallel
computation on short (length 2-8) vectors of integers or floats
Why do SIMD instructions (vector instructions) exist?
What is a FMA (Fused Multiply-Add)?
X = X+ V • Z
An add and a multiply done as one operation, i.e., involves only one rounding step which gives better accuracy than sequence of mult and add
This is a natural pattern in many algorithms
How big do the registers need to be to hold a 16-way single or an 8-way double?
16-way single is a vector with 16 floats
8-way double is a vector with 8 doubles
A double is 8 bytes = 64 bit.
So you need 512 bit registers to hold one of these vectors.
What is Microarchitecture?
Implementation of the architecture
Examples: Caches, cache structure, CPU frequency, details of the virtual
memory system
So those are either Intel processors or AMD processors.
If cache reads are slower than CPU why make such a fast CPU?
Because data can also be stored in registers.
Why can we forget about index computations for the runtime?
Because if the index computations are simple - if they are affine then they don't constitute a bottleneck.
What do Compute bound and Memory bound mean in terms of operational intensity?
A function/piece of code is:
Compute bound if it has high operational intensity
Memory bound if it has low operational intensity
What is a 2-way associative cache?
The cache is split into sets and if the cache contains two lines/blocks per set it is said to be 2-way associative.
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