System On Chip Technologies an der TU München | Karteikarten & Zusammenfassungen

Lernmaterialien für System on Chip Technologies an der TU München

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TESTE DEIN WISSEN
What is Noise Margin in CMOS?
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Measure of sensitivity of a gate to noise. The higher the better, information will still be processed correctly even with noise.
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TESTE DEIN WISSEN
How can higher speed circuits be obtained?
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TESTE DEIN WISSEN
Capacitive load, oxide thickness, channel length, and absolute threshold voltages have to be decreased, whereas carrier mobility, channel width, relative oxide dielectric, and supply voltage have to be increased.
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TESTE DEIN WISSEN
What are the steps to get a static CMOS logic design out of a logic function?
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1. Check the inverter function at the output, insert an inverter if necessary. 2. Start with the nMOS block from output to GND, use serial nMOS transistors for AND, parallel nMOS transistors for OR functions. 3. Continue with the pMOS block from the output to VDD, using the dual nMOS network and p-MOSFETs
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What timing restrictions apply when dealing with FlipFlops?
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TESTE DEIN WISSEN
The setup-time tsetup, the hold-time thold, and the clock-to-output delay tc2q. The first two parameters tsetup and thold impose restrictions on the input signal of the flip-flop. The input signal D must be stable for the setup-time before clock edge and for the hold-time after clock edge. Thisis required in order to guarantee correct setting of the flip-flop at the clock edge and to avoid metastability. The third parameter, tc2q, specifies the delay after the clock edge until the valid data will be visible at the output
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Name function density, frequency, one-time-cost, variable cost (chip area), typical volume and design time for Full Custom, Std Cell and FPGA
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Slide 39
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Where is the perfect spot in terms of flexibility/performance density in the chart on slide “Trade-Off: Flexibility vs. Performance” of the lecture handouts?
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TESTE DEIN WISSEN
The “perfect” point in the performance –flexibility coordinate system is the top right corner (maximum performance with maximum flexibility). (Whether it is feasible or realistic to obtain a solution that matches these properties is a different question.)
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Why is there no firm measure for Flexibility?
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TESTE DEIN WISSEN
Flexibility is difficult to quantify because there are various interpretations for flexibility. It’s an ongoing research topic to find a common measure for flexibility. Instruction depth is a starting point.
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Why is Computational Density typically related to Lmintiles and not to area measured in mm2?
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To maintain comparability between CMOS technology generations.
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Suppose your area budget is 1'000'000 Lmintiles. How many operations per second can you approximately get with an FPGA?
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From slide “Computational Density / Functional Diversity”: FPGA has a CD of around 400 ops / Lmintile. Hence 1 M tiles correspond to about 400 Million ops
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TESTE DEIN WISSEN
The result obtained in the previous question isn’t enough for your application at hand. You need at least 500Mops. Hence, your plan is to fill the 1 M Lmintiles with a mix of FPGA and another IC implementation technique. Which of the following three alternatives do you select under the constraint to maintain maximum flexibility? Alternatives are: CPU, ASIC, Custom IC.
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TESTE DEIN WISSEN
Trading FPGA against CPU area can only reduce the obtainable ops. Hence, ASIC or Custom IC has to be picked. Maximum flexibility (= most area filled with FPGA) is achieved with a mix of FPGA and Custom IC as Custom IC has highest CD per area. Thus, we need to give away least amount of the valuable (in terms of flexibility) FPGA area.Area = AFPGA+ ACUSTOM= 1'000'000 tilesPerformance = AFPGA*400 + ACUSTOM*10'000 >= 500'000'000 opsACUSTOM>= 10’417 tiles;(1% of total area make up for 20% of required performance)
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TESTE DEIN WISSEN
Order the following IC implementation methods according to increasing area densities and fixed costs: Gate Array, Full Custom, FPGA, Standard Cell
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Increasing area densities:FPGA, Gate Array, Standard Cell, Full Custom Increasing fixed costs: FPGA, Gate Array, Standard Cell, Full Custom
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TESTE DEIN WISSEN
What is CMOS Power Dissipation Density and how is it calculated?
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TESTE DEIN WISSEN
Power per Area, is proportional to the number of transistor devices per area, the switched gate-substrate capacity per device, the device operation frequency and the square of the supply voltage : P/A ~ N * C * f * V(dd)²
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Q:
What is Noise Margin in CMOS?
A:
Measure of sensitivity of a gate to noise. The higher the better, information will still be processed correctly even with noise.
Q:
How can higher speed circuits be obtained?
A:
Capacitive load, oxide thickness, channel length, and absolute threshold voltages have to be decreased, whereas carrier mobility, channel width, relative oxide dielectric, and supply voltage have to be increased.
Q:
What are the steps to get a static CMOS logic design out of a logic function?
A:
1. Check the inverter function at the output, insert an inverter if necessary. 2. Start with the nMOS block from output to GND, use serial nMOS transistors for AND, parallel nMOS transistors for OR functions. 3. Continue with the pMOS block from the output to VDD, using the dual nMOS network and p-MOSFETs
Q:
What timing restrictions apply when dealing with FlipFlops?
A:
The setup-time tsetup, the hold-time thold, and the clock-to-output delay tc2q. The first two parameters tsetup and thold impose restrictions on the input signal of the flip-flop. The input signal D must be stable for the setup-time before clock edge and for the hold-time after clock edge. Thisis required in order to guarantee correct setting of the flip-flop at the clock edge and to avoid metastability. The third parameter, tc2q, specifies the delay after the clock edge until the valid data will be visible at the output
Q:
Name function density, frequency, one-time-cost, variable cost (chip area), typical volume and design time for Full Custom, Std Cell and FPGA
A:
Slide 39
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Q:
Where is the perfect spot in terms of flexibility/performance density in the chart on slide “Trade-Off: Flexibility vs. Performance” of the lecture handouts?
A:
The “perfect” point in the performance –flexibility coordinate system is the top right corner (maximum performance with maximum flexibility). (Whether it is feasible or realistic to obtain a solution that matches these properties is a different question.)
Q:
Why is there no firm measure for Flexibility?
A:
Flexibility is difficult to quantify because there are various interpretations for flexibility. It’s an ongoing research topic to find a common measure for flexibility. Instruction depth is a starting point.
Q:
Why is Computational Density typically related to Lmintiles and not to area measured in mm2?
A:
To maintain comparability between CMOS technology generations.
Q:
Suppose your area budget is 1'000'000 Lmintiles. How many operations per second can you approximately get with an FPGA?
A:
From slide “Computational Density / Functional Diversity”: FPGA has a CD of around 400 ops / Lmintile. Hence 1 M tiles correspond to about 400 Million ops
Q:
The result obtained in the previous question isn’t enough for your application at hand. You need at least 500Mops. Hence, your plan is to fill the 1 M Lmintiles with a mix of FPGA and another IC implementation technique. Which of the following three alternatives do you select under the constraint to maintain maximum flexibility? Alternatives are: CPU, ASIC, Custom IC.
A:
Trading FPGA against CPU area can only reduce the obtainable ops. Hence, ASIC or Custom IC has to be picked. Maximum flexibility (= most area filled with FPGA) is achieved with a mix of FPGA and Custom IC as Custom IC has highest CD per area. Thus, we need to give away least amount of the valuable (in terms of flexibility) FPGA area.Area = AFPGA+ ACUSTOM= 1'000'000 tilesPerformance = AFPGA*400 + ACUSTOM*10'000 >= 500'000'000 opsACUSTOM>= 10’417 tiles;(1% of total area make up for 20% of required performance)
Q:
Order the following IC implementation methods according to increasing area densities and fixed costs: Gate Array, Full Custom, FPGA, Standard Cell
A:
Increasing area densities:FPGA, Gate Array, Standard Cell, Full Custom Increasing fixed costs: FPGA, Gate Array, Standard Cell, Full Custom
Q:
What is CMOS Power Dissipation Density and how is it calculated?
A:
Power per Area, is proportional to the number of transistor devices per area, the switched gate-substrate capacity per device, the device operation frequency and the square of the supply voltage : P/A ~ N * C * f * V(dd)²
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