System on Chip Technologies

Karteikarten und Zusammenfassungen für System on Chip Technologies an der TU München

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Lerne jetzt mit Karteikarten und Zusammenfassungen für den Kurs System on Chip Technologies an der TU München.

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

What LUT size (in bits) is necessary to realize two combinatorial functions (y and z) with up to four inputs (x1to x4)?

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

The result obtained in the previous question isn’t enough for your application at hand. You need at least 500Mops. Hence, your plan is to fill the 1 M Lmintiles with a mix of FPGA and another IC implementation technique. Which of the following three alternatives do you select under the constraint to maintain maximum flexibility? Alternatives are: CPU, ASIC, Custom IC.

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

Name differend kinds of Bus Arbitration Schemes!

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

Why isn’t it a contradiction that CPUs are full custom designs but have the lowest computational density compared to other implementation methods such as FPGAor standard cell ASIC?

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

What is the economic justification to design general purpose CPUs in the full custom implementation method? What is the technical justification to design the clock recovery logic of a 10 Gbit/s Ethernet transceiver interface in the full custom implementation method?

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

Order the following IC implementation methods according to increasing area densities and fixed costs: Gate Array, Full Custom, FPGA, Standard Cell

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

Power consumption limits the operation time per battery charge, but why is power important for stationary computers?

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

Clock gating saves dynamic power, but does not influence static power consumption. Why not always use power down with sleep transistors instead of clock gating?

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

Draw the Static Voltage Transfer Curve of a CMOS device.

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

What is the difference between 1-bit and 2-bit branch prediction?

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

Why is Computational Density typically related to Lmintiles and not to area measured in mm2?

Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

Suppose your area budget is 1'000'000 Lmintiles. How many operations per second can you approximately get with an FPGA?

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Beispielhafte Karteikarten für System on Chip Technologies an der TU München auf StudySmarter:

System on Chip Technologies

What LUT size (in bits) is necessary to realize two combinatorial functions (y and z) with up to four inputs (x1to x4)?
Four input function can access up to 2^4 = 16 different LUT locations. Two different outputs per LUT location results in a total memory requirement of 32bits.

System on Chip Technologies

The result obtained in the previous question isn’t enough for your application at hand. You need at least 500Mops. Hence, your plan is to fill the 1 M Lmintiles with a mix of FPGA and another IC implementation technique. Which of the following three alternatives do you select under the constraint to maintain maximum flexibility? Alternatives are: CPU, ASIC, Custom IC.
Trading FPGA against CPU area can only reduce the obtainable ops. Hence, ASIC or Custom IC has to be picked. Maximum flexibility (= most area filled with FPGA) is achieved with a mix of FPGA and Custom IC as Custom IC has highest CD per area. Thus, we need to give away least amount of the valuable (in terms of flexibility) FPGA area.Area = AFPGA+ ACUSTOM= 1’000’000 tilesPerformance = AFPGA*400 + ACUSTOM*10’000 >= 500’000’000 opsACUSTOM>= 10’417 tiles;(1% of total area make up for 20% of required performance)

System on Chip Technologies

Name differend kinds of Bus Arbitration Schemes!
Round Robin: Simple, but no Quality of Service support.
Strict Priotity: Simple, Starvation of low priority.
Weighted Priority: No starvation, Complex, no Bandwith guarantees
Weighted+Credits: QoS with BW guarantees, Complex control.

System on Chip Technologies

Why isn’t it a contradiction that CPUs are full custom designs but have the lowest computational density compared to other implementation methods such as FPGAor standard cell ASIC?
The computational density of a CPU relates to the program instruction sequence executed by the CPU. In order to execute a single instruction, the CPU has to perform a lot of preparation and coordination tasks (i.e., fetch instruction from memory, decode instructions, fetch operands) before the actual computation can be performed in one clock cycle. After the instruction computation, further “house keeping” is necessary to store the result for later reuse (register or memory write back cycle). Nevertheless, the effective use for the application is the computation which has been performed in a single instruction execution cycle. Hence, a (single-issue) microprocessor performs at best one N bit operation per clock cycle. However, the logic circuit area required to do so is the area of the entire CPU. That’s why CPUs have a low CD (computational density) although they are designed in full custom.

System on Chip Technologies

What is the economic justification to design general purpose CPUs in the full custom implementation method? What is the technical justification to design the clock recovery logic of a 10 Gbit/s Ethernet transceiver interface in the full custom implementation method?
Full custom designs require huge development teams and design effort due to the low level optimizations down to transistor level. This resultin a high upfront fixed cost one has to invest for a full custom design. Full custom designs require high volumes to amortize the huge one time fixed cost. General purpose processors are the prime example for components with extremely huge volume due to their broad application spectrum in various computing and “embedded systems” equipment.The other reason that justifies a full custom design method is when no other method achieves the required performance (speed) rate for a particular application. A 10 Gbit/s transceiver interface is a good example for a high performance function with high operating frequencies.

System on Chip Technologies

Order the following IC implementation methods according to increasing area densities and fixed costs: Gate Array, Full Custom, FPGA, Standard Cell
Increasing area densities:FPGA, Gate Array, Standard Cell, Full Custom
Increasing fixed costs: FPGA, Gate Array, Standard Cell, Full Custom

System on Chip Technologies

Power consumption limits the operation time per battery charge, but why is power important for stationary computers?
Power consumption heats up the chip. Removing the heat (ceramic chip housing, fan, liquid cooling) increases system costs.

System on Chip Technologies

Clock gating saves dynamic power, but does not influence static power consumption. Why not always use power down with sleep transistors instead of clock gating?
With clock gating all registers keep their information, whereas with power down all information is lost. Power down requires to save all necessary information and restore before power up. This takes additional time.

System on Chip Technologies

Draw the Static Voltage Transfer Curve of a CMOS device.
Slide 27

System on Chip Technologies

What is the difference between 1-bit and 2-bit branch prediction?
1-bit branch prediction only cares about the last outcome of a branch. They assume that the next outcome of a branch (taken or not taken) is the same as the previous one. They always guess wrong twice (beginning and exit)

2-bit branch predictors encode the state of each branch in the branch history table with 2 bits. Gets taken only if previous two times have been taken as well. Guesses wrong 1 time per anomaly, 2 times at behavior switch.

System on Chip Technologies

Why is Computational Density typically related to Lmintiles and not to area measured in mm2?
To maintain comparability between CMOS technology generations.

System on Chip Technologies

Suppose your area budget is 1'000'000 Lmintiles. How many operations per second can you approximately get with an FPGA?
From slide “Computational Density / Functional Diversity”: FPGA has a CD of around 400 ops / Lmintile. Hence 1 M tiles correspond to about 400 Million ops

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