System on Chip Technologies at TU München

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Study with flashcards and summaries for the course System on Chip Technologies at the TU München

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

What is the difference between 1-bit and 2-bit branch prediction?

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

What LUT size (in bits) is necessary to realize two combinatorial functions (y and z) with up to four inputs (x1to x4)?

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

Name 2 SoC busses! Name 2 examples for Throughput Improvements they use.

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

Can AMBA AXI perform split transfers?

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

Draw the Static Voltage Transfer Curve of a CMOS device.

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

Why isn’t it a contradiction that CPUs are full custom designs but have the lowest computational density compared to other implementation methods such as FPGAor standard cell ASIC?

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

Power consumption limits the operation time per battery charge, but why is power important for stationary computers?

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

Clock gating saves dynamic power, but does not influence static power consumption. Why not always use power down with sleep transistors instead of clock gating?

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

Name differend kinds of Bus Arbitration Schemes!

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

Which RAM-type do you select for: -a network processor with 4GByte of memory? -a single-chip search engine with a table size of 1024x1024 bit, access freq. of 300MHz required? -a single-chip search engine with a table size of 2048x1024 bit, access freq. of 100MHz required?

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

Order the following IC implementation methods according to increasing area densities and fixed costs: Gate Array, Full Custom, FPGA, Standard Cell

Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

What is the economic justification to design general purpose CPUs in the full custom implementation method? What is the technical justification to design the clock recovery logic of a 10 Gbit/s Ethernet transceiver interface in the full custom implementation method?

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Exemplary flashcards for System on Chip Technologies at the TU München on StudySmarter:

System on Chip Technologies

What is the difference between 1-bit and 2-bit branch prediction?
1-bit branch prediction only cares about the last outcome of a branch. They assume that the next outcome of a branch (taken or not taken) is the same as the previous one. They always guess wrong twice (beginning and exit)

2-bit branch predictors encode the state of each branch in the branch history table with 2 bits. Gets taken only if previous two times have been taken as well. Guesses wrong 1 time per anomaly, 2 times at behavior switch.

System on Chip Technologies

What LUT size (in bits) is necessary to realize two combinatorial functions (y and z) with up to four inputs (x1to x4)?
Four input function can access up to 2^4 = 16 different LUT locations. Two different outputs per LUT location results in a total memory requirement of 32bits.

System on Chip Technologies

Name 2 SoC busses! Name 2 examples for Throughput Improvements they use.
PLB Processor Local Bus
ARM AMBA Advanced Microcontroller Bus Architecture

– Pipelines
– Indepented busses for read/write

System on Chip Technologies

Can AMBA AXI perform split transfers?
Yes, split transfers are a particular case of out-of-order transfers which AXI is capable of.

System on Chip Technologies

Draw the Static Voltage Transfer Curve of a CMOS device.
Slide 27

System on Chip Technologies

Why isn’t it a contradiction that CPUs are full custom designs but have the lowest computational density compared to other implementation methods such as FPGAor standard cell ASIC?
The computational density of a CPU relates to the program instruction sequence executed by the CPU. In order to execute a single instruction, the CPU has to perform a lot of preparation and coordination tasks (i.e., fetch instruction from memory, decode instructions, fetch operands) before the actual computation can be performed in one clock cycle. After the instruction computation, further “house keeping” is necessary to store the result for later reuse (register or memory write back cycle). Nevertheless, the effective use for the application is the computation which has been performed in a single instruction execution cycle. Hence, a (single-issue) microprocessor performs at best one N bit operation per clock cycle. However, the logic circuit area required to do so is the area of the entire CPU. That’s why CPUs have a low CD (computational density) although they are designed in full custom.

System on Chip Technologies

Power consumption limits the operation time per battery charge, but why is power important for stationary computers?
Power consumption heats up the chip. Removing the heat (ceramic chip housing, fan, liquid cooling) increases system costs.

System on Chip Technologies

Clock gating saves dynamic power, but does not influence static power consumption. Why not always use power down with sleep transistors instead of clock gating?
With clock gating all registers keep their information, whereas with power down all information is lost. Power down requires to save all necessary information and restore before power up. This takes additional time.

System on Chip Technologies

Name differend kinds of Bus Arbitration Schemes!
Round Robin: Simple, but no Quality of Service support.
Strict Priotity: Simple, Starvation of low priority.
Weighted Priority: No starvation, Complex, no Bandwith guarantees
Weighted+Credits: QoS with BW guarantees, Complex control.

System on Chip Technologies

Which RAM-type do you select for: -a network processor with 4GByte of memory? -a single-chip search engine with a table size of 1024x1024 bit, access freq. of 300MHz required? -a single-chip search engine with a table size of 2048x1024 bit, access freq. of 100MHz required?
-A network processorwith 4GByte of memory:4GByte => need to go off-chip (today max. 4GBit/chip). No speed constraint given in this example => cheapest and densest is external SDRAM.
-A single-chip search engine with a table size of 1024×1024 bit, access freq. of 300MHz required: 300MHz (3.3 ns cycle time) can only be reached with on-chip SRAM. 1Mbit on-chip SRAM is possible.
–> A single-chip search engine with a table size of 2024×1024 bit, access freq. of 100 MHz required: If you have access to an advanced CMOS process, embedded DRAM would be the best choice. The 10ns (random) access latency can be met with eDRAM. eDRAM is much denser than on-chip SRAM (2Mbits are no problem). Suggesting on-chip SRAM is the second best choice (although more expensive in area).

System on Chip Technologies

Order the following IC implementation methods according to increasing area densities and fixed costs: Gate Array, Full Custom, FPGA, Standard Cell
Increasing area densities:FPGA, Gate Array, Standard Cell, Full Custom
Increasing fixed costs: FPGA, Gate Array, Standard Cell, Full Custom

System on Chip Technologies

What is the economic justification to design general purpose CPUs in the full custom implementation method? What is the technical justification to design the clock recovery logic of a 10 Gbit/s Ethernet transceiver interface in the full custom implementation method?
Full custom designs require huge development teams and design effort due to the low level optimizations down to transistor level. This resultin a high upfront fixed cost one has to invest for a full custom design. Full custom designs require high volumes to amortize the huge one time fixed cost. General purpose processors are the prime example for components with extremely huge volume due to their broad application spectrum in various computing and “embedded systems” equipment.The other reason that justifies a full custom design method is when no other method achieves the required performance (speed) rate for a particular application. A 10 Gbit/s transceiver interface is a good example for a high performance function with high operating frequencies.

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